The present invention relates to a normally-off electrical circuit with low on-resistance and particularly to such a circuit suitable for power switching applications.
A prior art junction field effect transistor (JFET) of the N-channel type typically comprises a channel region of N-type semiconductor material and a P-type gate region adjoining the N-type channel region and forming a P-N junction therewith. Upon reverse biasing of this P-N junction through appropriate biasing of the P-type gate region, a depletion region is formed in the N-type channel region in the vicinity of the P-N junction and extends into the channel region so as to shrink the portion of the channel that can conduct current. When the depletion region has spread across the entire channel, the JFET is in, what is known in the art, as a pinched-off condition in which it cannot conduct current.
A JFET is a normally-on or -conducting device; that is, a JFET's gate region must be actively biased in order to pinch off the JFET and terminate current conduction through the device. In many applications, however, it is desirable to have normally-off device operation. Such normally-off operation is achieved in an electrical circuit described and claimed in copending U.S. patent application Ser. No. 257,080, filed 24 April, 1981 by B. J. Baliga (the present inventor) and M. S. Adler, and assigned to the present assignee. In such circuit, a JFET is serially connected to a bipolar transistor, with the base electrode of the bipolar transistor serving as a gate or control electrode for the entire circuit. Normally-off operation of the JFET is achieved because the base electrode must be appropriately biased to turn on the bipolar transistor and allow the JFET to conduct current.
In the foregoing electrical circuit, the gate of the JFET is electrically shorted to the emitter of the bipolar transistor, resulting in the P-N junction of the JFET being reverse-biased, at least to a slight extent, while the JFET is conducting current. As a consequence, the circuit cannot take advantage of a technique for markedly lowering the on-resistance of a JFET, which requires forward-biasing of the P-N junction of the JFET. In a JFET having its P-N junction sufficiently forward-biased so as to utilize this technique, the JFET's P-type gate region injects holes into the N-type channel region which already contains electrons, whereby the JFET operates in a bipolar conduction mode. This results in a lowering of the channel resistance, and hence the on-resistance of the JFET. By controlling the level of the biasing voltage on the JFET's gate, the extent of carrier injection into the N-type channel and, hence, the on-resistance of the JFET, is modulated. This technique is discussed in detail in an article by B. J. Baliga, entitled "Bipolar Operation of Power Junction Gate Field-Effect-Transistors", Electron Letters, Vol. 16 (1980), pages 300-301 which is incorporated herein by reference.
It would be desirable to provide an electrical circuit including a JFET and operating in a normally-off fashion, yet which utilizes the foregoing technique for achieving a markedly reduced on-resistance by means of forward-biasing its P-N junction.